The principle of operation of the kmop circuit. The elemental base of various logics: schemes, TTL, TTL, kmop

A good example of how complicated everything is in confusing in determining the priorities of scientific research is CMOS chips and their appearance on the market.

The fact is that the field effect that underlies the MOS structure was discovered back in the late 20s of the last century, but then radio engineering was experiencing a boom in vacuum devices (radio tubes) and the effects found in crystalline structures were considered unpromising.

Then, in the 40s, the bipolar transistor was practically reopened, and only then, when further studies and improvements of bipolar transistors showed that this direction leads to a dead end, scientists remembered the field effect.

So there was a MOS transistor, and later CMOS chips. Letter TO at the beginning of the abbreviation means complementary, that is, complementary. In practice, this means that microcircuits use pairs of transistors with exactly the same parameters, but one transistor has an n-type gate, and the other transistor has a p-type gate. In a foreign manner, CMOS chips are called CMOS (Complementary Metal-Oxide Semiconductor). Also abbreviations KMDP, K-MOS.

Among conventional transistors, an example of a complementary pair is the KT315 and KT361 transistors.

First, the K176 series based on field-effect transistors appeared on the market of electronic components, and, as a further development of this series, the very popular K561 series was developed. This series includes a large number of logic chips.

Since field effect transistors are not as critical to the supply voltage as bipolar ones, this series is powered by voltage from +3 to + 15V. This allows you to widely use this series in various devices, including battery-powered. In addition, devices assembled on K561 series chips consume very little current. And it’s not surprising, because the basis of CMOS chips is an MOSFET.

For example, the K561TP2 chip contains four RS-flip-flops and consumes 0.14 mA current, and a similar K155 series chip consumed a minimum of 10 - 12 mA. Chips on CMOS structures have a very large input impedance, which can reach 100 MΩ or more, therefore their load capacity is quite large. To the output of one chip, you can connect the inputs of 10 to 30 chips. For TTL microcircuits, such a load would cause overheating and failure.

Therefore, the design of nodes on microcircuits using CMOS transistors allows the use of simpler circuit solutions than when using TTL microcircuits.

Abroad, the most common analogue of the K561 series is labeled as CD4000. For example, the K561LA7 chip corresponds to a foreign CD4011.

Using chips of the K561 series, one should not forget about some of the nuances of their operation. It should be remembered that although the microcircuit is operable in a wide voltage range, noise immunity decreases with a decrease in the supply voltage, and the pulse slightly “spreads out”. That is, the closer the supply voltage is to the maximum, the steeper the edges of the pulses.

The figure shows a classic basic element (valve) that inverts the input signal (element NOT). That is, if a logical unit arrives at the input, then a logical zero is removed from the output and vice versa. Here, a complementary pair of transistors with gates of "n" and "p" types is clearly shown.

The following figure shows the basic element 2I - NOT. It is clearly seen that the resistors that are present in a similar element of the TTL chip are missing. It’s easy to get a trigger from two of these elements, and from a sequential series of triggers there is a direct road to counters, registers, and storage devices.

With all the positive qualities of the integrated circuits of the K561 series, they, of course, have drawbacks. Firstly, according to the maximum working frequency of CMOS, microcircuits are noticeably inferior to microcircuits with different logic and operating on bipolar transistors.

The frequency at which the K561 series confidently works does not exceed 1 MHz. To harmonize microcircuits based on MOS structures with other series, for example, TTL, K561PU4, K561LN2 level converters and others are used. These chips also synchronize performance, which may vary for different series.

But the biggest drawback of microcircuits on complementary MOS structures is the strong sensitivity of the microcircuit to static electricity. Therefore, special workplaces are equipped in factories and laboratories. On the table, all work is done on a metal sheet that is connected to a common ground bus. Both the soldering iron body and the metal bracelet worn on the employee’s hand are connected to this bus.

Some microcircuits go on sale packaged in foil, which shorts all the outputs together. When working at home, it is also necessary to find an opportunity for draining static charge at least to the heating pipe. During installation, the power leads are first soldered, and then all the others.

CMOS Logic Inverters

Microchips based on complementary MOS transistors (CMOS chips) are built on the basis of MOS transistors with n- and p-channels. The same input potential opens the transistor with the n-channel and closes the transistor with the p-channel. When forming a logical unit, the upper transistor is open, and the lower one is closed. As a result, no current flows through the CMOS circuit. When forming a logical zero, the lower transistor is open, and the upper one is closed. And in this case, the current from the power source does not flow through the microcircuit. The simplest logic element is the inverter. an inverter made on complementary MOS transistors is shown in Figure 1.

Figure 1. Schematic diagram of an inverter made on complementary MOS transistors (CMOS inverter)

As a result of this feature of CMOS chips, they have an advantage over the types considered earlier - they consume current depending on the clock frequency applied to the input. An approximate graph of the current consumption of a CMOS chip depending on its switching frequency is shown in Figure 2

Figure 2. The dependence of the current consumption of the CMOS chip on the frequency

Logical CMOS (KMDP) elements And

The logic circuit "AND NOT" on CMOS chips, it almost coincides with the simplified "I" circuit on the keys with electronic control, which we considered earlier. The difference is that the load is connected not to the common circuit wire, but to the power source. Schematic diagram of the logic element "2I-NOT", made on complementary MOS transistors (CMOS), shown in Figure 3.

Figure 3. Schematic diagram of the logic element "2I-NOT", made on complementary MOS transistors (CMOS)

In this circuit, one could use the ordinary one in the upper arm, however, when a low signal level was formed, the circuit would constantly consume current. Instead, p-MOS transistors are used as the load. These transistors form an active load. If the output requires the formation of a high potential, then the transistors open, and if low, they close.

In the circuit of the “And” logic CMOS element shown in Figure 2, the current from the power source to the output of the CMOS chip will flow through one of the transistors if at least one of the inputs (or both at once) has a low potential (logic level zero). If the logic unit level is present at both inputs of the CMOS logic element “AND”, then both p-MOS transistors will be closed and a low potential will form at the output of the CMOS chip. In this circuit, as well as in the circuit shown in Figure 1, if the upper arm transistors are open, the lower arm transistors will be closed, therefore, in a static state, the current CMOS chip from the power source will not be consumed.

The CMOS of the 2I-NOT logical element is shown in Figure 4, and the truth table is shown in Table 1. In Table 1, the inputs are marked as x 1 and x 2, and the output is F.

Figure 4. Conditionally-graphic image of the logical element "2 AND NOT"

Table 1. The truth table of a CMOS chip that performs "2I-NOT"

x1	x2	F
0	0	1
0	1	1
1	0	1
1	1	0

"OR", made on CMOS transistors, is a parallel connection of keys with electronic control. The difference from the simplified “2OR” circuit, considered earlier, is that the load is connected not to the common circuit wire, but to the power source. Instead of a resistor, p-MOS transistors are used as a load. Schematic diagram of the logic element "2OR-NOT", made on complementary MOS transistors is shown in Figure 5.

Figure 5. Schematic diagram of the logic element "OR NOT", performed on complementary MOS transistors

In the CMOS circuit of the "2OR-NOT" logic element, p-MOS transistors connected in series are used as the load. In it, the current from the power source to the output of the CMOS chip will only come if all the transistors in the upper arm are open, i.e. if all potential inputs have low potential () at once. If at least one of the inputs contains a logic level, the upper arm of the push-pull cascade assembled on CMOS transistors will be closed and the current from the power source will not be output to the CMOS chip.

The truth table of the "2OR-NOT" logical element implemented by the CMOS chip is shown in Table 2, and the graphic designation of these elements is shown in Figure 6.

Figure 6. Element "2 OR NOT"

Table 2. The truth table of the MOS chip that performs the logical function "2OR-NOT"

x1	x2	F
0	0	1
0	1	0
1	0	0
1	1	0

At present, it is CMOS chips that have received the greatest development. Moreover, there is a constant tendency to reduce the supply voltage of these microcircuits. The first series of CMOS chips, such as K1561 (a foreign analog of the C4000V), had a fairly wide range of variation in the supply voltage (3..18V). At the same time, with a decrease in the supply voltage, a specific microcircuit decreases its maximum operating frequency. In the future, as production technology improved, improved CMOS chips appeared with better frequency properties and lower supply voltage, for example, SN74HC.

Features of the use of CMOS chips

The first and main feature of CMOS chips is the high input impedance of these chips. As a result, any voltage can be induced at its input, including one equal to half the supply voltage, and be stored on it for a sufficiently long time. When half the power supply is applied to the input of the CMOS element, transistors open both in the upper and lower arms of the output stage, as a result, the microcircuit starts to consume an unacceptably high current and may fail. Conclusion: the inputs of digital CMOS chips should never be left unconnected!

The second feature of CMOS chips is that they can work when the power is off. However, they work most often incorrectly. This feature is associated with the design of the input stage. The complete circuit diagram of the CMOS inverter is shown in Figure 7.

Figure 7. Complete circuit diagram of a CMOS inverter

Diodes VD1 and VD2 were introduced to protect the input stage from breakdown by static electricity. At the same time, when a high-potential CMOS chip is supplied to the input, it will go through the VD1 diode to the power supply bus of the microcircuit, and since it consumes a fairly small current, the CMOS microcircuit will begin to work. However, in some cases, this current may not be enough to power the chips. As a result, the CMOS chip may not work properly. Conclusion: if the CMOS chip is not working properly, carefully check the power of the chip, especially the findings of the case. With a poorly soldered negative power output, its potential will differ from the potential of the common circuit wire.

The fourth feature of CMOS microcircuits & mdash is the flow of pulsed current through the power circuit when it switches from zero to a single state and vice versa. As a result, when switching from TTL microcircuits to CMOS microcircuit analogs, the level of interference sharply increases. In some cases, this is important, and one has to abandon the use of CMOS chips in favor or BICMOS chips.

CMOS logic levels

The logical levels of CMOS chips are significantly different from. In the absence of a load current, the voltage at the output of the CMOS chip coincides with the supply voltage (logical unit level) or with the potential of the common wire (logical zero level). With an increase in the load current, the voltage of the logical unit can decrease to 2.8 V (U p \u003d 15 V) from the supply voltage. The permissible voltage level at the output of the digital CMOS microcircuit (K561 series of microcircuits) with five-volt power is shown in Figure 8.

Figure 8. The levels of logical signals at the output of digital CMOS chips

As mentioned earlier, the voltage at the input of a digital microcircuit in comparison with the output is usually allowed within wide limits. For CMOS chips, we agreed on a 30% margin. The boundaries of the levels of logical zero and unity for CMOS chips with five-volt power are shown in Figure 9.

Figure 9. Levels of logic signals at the input of digital CMOS chips

With a decrease in the supply voltage, the boundaries of the logical zero and the logical unit can be determined in the same way (divide the supply voltage by 3).

CMOS chip families

The first CMOS microcircuits did not have protective diodes at the input, so their installation was very difficult. This is a K172 series chip family. The next improved CMOS family of K176 series chips received these protective diodes. It is quite common at the present time. The K1561 series completes the development of the first generation of CMOS chips. In this family, performance was achieved at the level of 90 ns and the range of variation of the supply voltage was 3 ... 15 V. Since foreign equipment is currently common, I will give a foreign analog of these CMOS chips - C4000V.

A further development of CMOS chips was the SN74HC series. These microcircuits do not have a domestic analogue. They have a speed of 27 ns and can operate in the voltage range of 2 ... 6 V. They coincide in the pinout and functional range with, but are not compatible with them in logical levels, therefore, CMOS chips of the SN74HCT series were developed at the same time (domestic counterpart - K1564) compatible with TTL chips and logic levels.

At this time, there was a transition to a three-volt power supply. For it, the SN74ALVC CMOS chips were developed with a signal delay time of 5.5 ns and a power range of 1.65 ... 3.6 V. These same microcircuits are also capable of working with 2.5 volt power. The delay time of the signal increases to 9 ns.

The most promising family of CMOS chips is currently considered the SN74AUC family with a signal delay time of 1.9 ns and a power range of 0.8 ... 2.7 V.

The basis of CMOS elements is an inverter built on two complementary (complementary) MOS transistors ( n-MOS and p-MOS) with an isolated gate and an induced channel. A feature of such a scheme ( fig. 4.17) is that the input voltage controls not only the key, but also the load transistor.

On fig. 4.5.2.the gate-gate characteristics of the used transistors are given. Transistor with n-channel ( VT n) starts to conduct current if a positive voltage is applied to its gate, and the transistor with r-channel ( VT p) - if a negative voltage is applied to its gate with respect to the source.

It is important that both transistors have a heel on their drain-gate characteristics. Thus, if we want the circuit to operate at a positive supply voltage (+ E P), then as a key transistor it is necessary to use VT n, and as a load - VT p.

Fig. 4.17.1. CMOS inverter

Fig. 4.5.2. CMOS transistors

Inverter ( fig. 4.17) is constructed so that the source VT p is connected to E nand the source VT n - with the ground. Shutters VT nand VT p combine and serve as the input of the inverter, drains VT nand VT p are also combined and serve as the output of the inverter. With this inclusion, the following formulas will be valid for determining the gate-source voltage VT nand VT p: U zip \u003d U in, U zir \u003d U in -E p

U zip - gate-source voltage nchannel transistor ( VT n);

U zir- gate-source voltage rchannel transistor ( VT r).

When considering the operation of the inverter, we will assume that VT nand VT p have identical characteristics and threshold voltage U PP \u003d½ U ol½ \u003d 1.5V.

U pp- threshold voltage nchannel transistor;

U ol- threshold voltage pchannel transistor.

Consider the operation of the CMOS inverter by its HVV ( fig. 4.18-a), in which four sections and dependencies can be distinguished U ZI = f(U bx) (fig. 4.18-b).

Section 1: U 0 bx £ U. Wherein U zip \u003d U in and VT n closed U zir \u003d U in - E p< U oland VT p open.

Fig. 4.18. CMOS inverter features:
a) CVB, b) U SHUTTER-SOURCE \u003d f (U ВХ); c) I POST \u003d f (U BX)

VT nclosed) VT p is in deep saturation, while the output will have a voltage close to E P ( U 1 EXIT » E P).

Section II: U P\u003e U BX\u003e U PP,

where U P - voltage at which circuit switching occurs

and U OUT \u003d 0.5 (U 1 - U 0). U SPTA \u003d U IN\u003e U PPand VT nstarts to open U ZIR \u003d U BX-E P< U Пр and VT p is open.

On this site ½ U SPTA½ < ½ U ZIR½, therefore VT p will remain saturated, and VT n - in active mode.

VT n.

The current flowing in the circuit creates a voltage drop on the channel VT p, due to this, the output voltage begins to decrease. However, with increasing input voltage in this section, the output voltage decreases slightly, since VT p is still in saturation.

Point U P: U BX \u003d U P \u003d 0.5E P;

U SPTA \u003d U BX \u003d U P\u003e U PP, and VT n open 0.5E P< U Пр and VT p is open.

At this point | U SPTA|=|U ZIR| therefore, the resistance of the channels of both transistors are equal. Thus, the output will be a voltage equal to half the voltage of the power source ( U EXIT=0,5E P). This point corresponds to a vertical section on the characteristic. At this point, the circuit draws maximum current, since both transistors are open. At the slightest change in the input voltage, the output voltage changes dramatically.

Section III: E P -½ U ol½ \u003e U BX\u003e U P; U SPTA= U BX\u003e U PP and VT nopen U ZIR \u003d U BX-E P< U Пр and VT P is open, but with growth U BX becoming less and less open.

On this site U SPTA\u003e|U ZIR|, and therefore VT nis saturated, a VT p - in active mode.

The current consumed by the circuit is determined in this case by a transistor VT p.

The output voltage in this section is equal to the voltage drop across the channel VT n. Because VT nis saturated, then this drop is small, and with growth U bx it is decreasing more and more.

Section IV: E p\u003e U I\u003e E p -½ U ol½; U zip= U I\u003e U PP and V nopen U zir \u003d U in -E n\u003e U zipand VT p is closed.

In this state, the circuit practically does not consume current (since VT p is closed). VT nis in deep saturation, while the output will have a voltage close to zero ( U out» 0).

As seen from the HVV ( fig 4.5.1a), CMOS elements have good noise immunity. Noise immunity equal to zero and one. This is because the switching point ( U I \u003d U P) lies exactly in the center of the input voltage range ( E P\u003e U I\u003e0). At E P \u003d + 5V maximum interference value can reach 1.5V. With growth E P absolute noise immunity increases. Interference immunity of CMOS elements is approximately 30% of E P (U 0 input max»0.3 E P, U 1 int.min0.7 E P).

Since MOSFETs with an insulated gate are installed at the input of the CMOS inverter, the input resistance is very large (10 12 ¸10 13 Ohms). Therefore, such circuits practically do not consume current at the input.

The output impedance of CMOS circuits is small as in the state Log. 0, and in the state Log. 1, since one of the transistors VT n or VT p will definitely be open. Thus, the output resistance is determined by the channel resistance of the open MOS transistor and is 10 2 ¸ 10 3 Ohms.

High input and low output impedances cause a high static output branching coefficient. The branching coefficient will be limited from above only by performance requirements. Since each input of the circuit has a specific capacity, with increasing branching coefficient, the load capacitance will increase, which, in turn, will increase the switching time of the element.

Thus, with a decrease in the operating frequency, the branching coefficient will increase. In connection with the foregoing, it is clear that the input and load characteristics lose their meaning. The load characteristic is relevant only when pairing the CMOS elements with elements of other types.

The low output impedance of the element in both states allows you to quickly recharge the load capacitance. This leads to short delay times when turning the circuit on and off. In practice, the delay times are 50 ¸ 200 ns.

Fig. 4.5.1c explains the process of current consumption by the circuit.

In the static position, CMOS circuits consume a very small current (10 -6 -10 -7 A).

Mostly current is consumed when switching the circuit, while U SPTAand ½ U ZIR½> U POR and both transistors VT n and VT p open (sections II and III on the HVV) However, the magnitude of this current is less than that of TTL circuits, since the volume resistance of open MOS transistors exceeds the resistance of open bipolar transistors. For this reason, there is no limiting resistor in CMOS circuits.

When switching the circuit, current is also consumed to charge the load capacitance. The magnitude of this current can be defined as I \u003d CEf P Where f P - frequency switching circuit.

The advantages of CMOS circuits can also include the ability to work with different supply voltages (3-15V). With increasing supply voltage, the absolute noise immunity will increase, but the current consumption will also increase (sections II and III on the HVV will become wider). With a supply voltage of + 5V, the signal levels of the CMOS circuits become compatible with the TTL levels. U 1 in.min for CMOS circuits would be more E P - |U OL | for reliable locking VT p. For this purpose, often the TTL output through a resistor is connected to E P.

The work of CMOS circuits on TTL circuits is carried out, as a rule, through wiring diagrams.

On fig. 4.19a diagram of the basic element of the CMOS type is given. The element implements the 4I-NOT function. Transistors are arranged so that for any combination of input signals in the circuit there will be no flow of through current. In a similar way, elements of the OR-NOT type are constructed (fig. 4.20).

In such circuits, due to the series connection of transistors in one of the arms, the output resistance in one of the states increases. Therefore, such elements have different on and off times. For an AND-NOT element, the turn-on time is longer than the turn-off time, and for an AND-NOT element, vice versa.

Fig. 4.19. Implementation of the 4-NOT function on CMOS

Fig. 4.20. Implementing 4-OR-NOT CMOS

Due to the very high input impedance, even a static charge can create breakdown voltage. To protect against high-voltage charges of static electricity at the inputs of the CMOS circuits there is (inside the chip) a special protection circuit (fig. 4.21).

Fig. 4.21. CMOS inverter with shutter protection against static electricity

Diodes VD1, VD2 and Vd3 protect shutter insulation from breakdown. Diodes Vd4 and Vd7 protect the inverter output from breakdown between r and n areas. Diodes Vd5 and Vd6 connected in series between the power rails to protect against accidental polarity reversal.

Typical representatives of CMOS circuits are elements of the K564 series, which are characterized by the following parameters:

E P\u003d 3¸15V; U 0\u003d 0.01V (at E P\u003d 5V and I n=0); U 1\u003d 4.99V (at E P\u003d 5V and I n=0); I 0 input\u003d 0.2 μA; I 1 in\u003d 0.2 μA; I P\u003d 0.17mA (at E P\u003d 10V, F\u003d 100kHz and With n\u003d 50pF); t s\u003d 80ns; I 0 out\u003d 0.9mA (at U 0 out\u003d 0.5V and E P\u003d 10V); I 1 out\u003d 0.9mA (at U 1 out=E P-0.5V and E P\u003d 10V); C n \u003d200pF; C in\u003d 12pF.

Particular attention in the preparation requires an individual experiment (UIRS).

INTRODUCTION

Let's talk about the characteristics of an ideal family of logic chips. They should not dissipate power, have zero signal propagation delay, controlled rise and fall times of the signal, and also have noise immunity equivalent to 50% of the output signal span.

The parameters of modern families of CMOS chips (complementary MOS) are approaching these ideal characteristics.

First, CMOS circuits dissipate low power. The typical value of the static power dissipation is about 10 nV per valve, which is formed by leakage currents. Active (or dynamic) power dissipation depends on the voltage of the power source, frequency, output load and rise time of the input signal, but its typical value for one valve at a frequency of 1 MHz and a load with a capacity of 50 pF does not exceed 10 mW.

Secondly, although the propagation delay time of the signal in the CMOS valves, although not non-zero, is small enough. Depending on the voltage of the power supply, the signal propagation delay for a typical cell is in the range of 25 to 50 ns.

Third, rise and fall times are controllable, and are more linear than step functions. Typically, rise and fall times are 20–40% larger than the propagation delay time.

And finally, the typical value of noise immunity approaches 50% and is approximately 45% of the amplitude of the output signal.

Another important factor that testifies in favor of CMOS chips is their low cost, especially when used in portable equipment powered by low-power batteries.

Power supplies in systems built on CMOS microcircuits can be low-power, and, as a result, inexpensive. Due to the low power consumption, the power subsystem can be simpler, which means cheaper. Radiators and fans are not needed due to the low power dissipation. Continuous improvement of technological processes, as well as an increase in production volumes and expansion of the range of manufactured CMOS chips, leads to a decrease in their cost.

There are many series of CMOS logic chips. The first of them was the K176 series, then K561 (CD4000AN) and KP1561 (CD4000BN), but the most developed functional series were in the series KP1554 (74ACxx), KP1564 (74HCxx) and KP1594 (74ACTxx).

The functional series of modern CMOS chips of the КР1554, КР1564 and КР1594 series contain full-featured equivalents of the TTLSh-series chips КР1533 (74ALS) and К555 (74LS), which completely coincide both in the functions performed and in the pinout (pinout). Modern CMOS microcircuits, in comparison with their prototypes, K176 and K561 series, consume significantly less dynamic power and are many times superior to them in speed.

To simplify the circuitry, CMOS series with an input threshold voltage of TTL levels (KR1594 and some others) and CMOS levels (KR1554, KR1564 and some others) have been developed. The operating temperature range for general-purpose microcircuits is within the range of -40- + 85С, and -55- + 125С - for special applications. In the table. Figure 1 shows a comparison of the input and output characteristics of CMOS and TTLS-chips.

Table 1. Comparison of the electrical parameters of CMOS and TTLS-schemes

TECHNOLOGY	CMOS with PAC shutter	Improvement. CMOS with PAC shutter	CMOS with Metal Shutter	Stan dart.	Low-consuming TTLSH	Improved Low-Power TTLS	Fast acting TTLSH


Power dissipation per gate (mW)
Static
At a frequency of 100 kHz
Propagation Delay Time (ns) (CL \u003d 15 pF)
Maximum clock speed (MHz) (CL \u003d 15 pF)
Minimum Output Current (mA)
Standard outputs

Output branching ratio (Load on one input K555)
Standard outputs
High Load Outputs
Maximum input current, IIL (mA) (VI \u003d 0.4 V)

CMOS CHARACTERISTICS

The purpose of this section is to give the system designer the necessary information about how digital microcircuits of the CMOS structure work and behave when exposed to various control signals. Quite a lot has been written about the design and production technology of CMOS chips, so here we only consider the circuitry features of this family of chips.

The main CMOS circuit is the inverter shown in fig. 1. It consists of two field-effect transistors operating in the enrichment mode: with a P-type channel (upper) and an N-type channel (lower). To indicate power pins, the following are accepted: VDD or VCC for positive output and VSS or GND for negative. The designations VDD and VCC are derived from conventional MOS circuits and symbolize the power sources of the source and drain of transistors. They are not directly related to CMOS circuits, since the power leads are the sources of both complementary transistors. VSS or GND designations are derived from TTL circuits, and this terminology has been retained for CMOS circuits. The designations VCC and GND will be indicated below.

The logical levels in a CMOS system are VCC (logical “1”) and GND (logical “0”). Since the current flowing in the “on” MOS transistor practically does not create a voltage drop on it, and since the input resistance of the CMOS valve is very large (the input characteristic of the MOS transistor is mainly capacitive and looks like a current-voltage characteristic of the MOS transistor with a resistance of 1012 Ohms shunted by a capacitor with a capacity of 5 pF), then the logic levels in the CMOS system will be almost equal to the voltage of the power source.

Now let's look at the characteristic curves of MOS transistors in order to get an idea of \u200b\u200bhow the rise and fall times, signal propagation delays and power dissipation will change with changing power supply voltage and load capacitance.

In fig. Figure 2 shows the characteristic curves of the N-channel and P-channel field effect transistors operating in the enrichment mode.

A number of important conclusions follow from these characteristics. Consider a curve for an N-channel transistor with a Gate-Source voltage equal to VGS \u003d 15 V. It should be noted that for a constant control voltage VGS, the transistor behaves like a current source for VDS (Stoke-Source voltage) values \u200b\u200bgreater than VGS-VT (VT threshold voltage of the MOS transistor). For VDS values \u200b\u200bless than VGS-VT, the transistor behaves basically like a resistor.

It should also be noted that for smaller VGS values, the curves are of a similar nature, except that the IDS value is much smaller and, in fact, IDS increases in proportion to the VGS square. A P-channel transistor has almost the same, but complementary (complementary) characteristics.

In the case of capacitive load control using CMOS elements, the initial change in the voltage applied to the load will be linear, due to the “current” characteristic in the initial section, obtained by rounding the prevailing resistive characteristic, when the VDS value differs little from zero. With reference to the simplest CMOS inverter shown in Fig. 1, as the VDS voltage decreases to zero, the output voltage VOUT will tend to VCC or GND, depending on whether the transistor is open: P-channel or N-channel.

If you increase VCC, and therefore VGS, the inverter must develop a large voltage amplitude on the capacitor. However, for the same voltage increment, the load capacity of IDS increases sharply, like the VGS square, and therefore the rise times and propagation delays of the signal shown in Fig. 3 are decreasing.

Thus, it can be seen that for this design, and, therefore, a fixed value of the load capacitance, an increase in the voltage of the power supply will increase the speed of the system. Increasing VCC will increase performance, but also power dissipation. This is true for two reasons. Firstly, the product CV2f, which means power, is increasing. This is the power dissipated in the CMOS circuit, or any similar circuit, for the reason mentioned above, when controlling capacitive load.

For the indicated values \u200b\u200bof the load capacitance and switching frequency, the dissipated power increases in proportion to the square of the voltage drop across the load.

The second reason is that the product VI or the power dissipated in the CMOS circuit increases with the voltage of the VCC power supply (for VCC\u003e 2VT). Each time, when the circuit switches from one state to another, a short-term flowing current occurs, flowing from VCC to GND through two simultaneously open output transistors.

Since the threshold voltages of the transistors do not change with increasing VCC, the input voltage range within which the upper and lower transistors are simultaneously in a conducting state increases with increasing VCC. At the same time, a higher VCC value provides higher VGS control voltages, which also lead to an increase in JDS currents. In this regard, if the rise time of the input signal is zero, then through the output transistors there would be no through current from VCC to GND. These currents arise because the edges of the input signal have of course small rise and fall times, and therefore, the input voltage requires a certain finite short time to go through a range in which two output transistors are turned on simultaneously. Obviously, the rise and fall times of the edges of the input signal should have a minimum value to reduce the power dissipation.

Let's take a look at the transfer characteristics (Fig. 5), how they change with a change in the supply voltage VCC. We agree that both transistors in our simplest inverter have identical but complementary characteristics and threshold voltages. Assume that the threshold voltages, VT, are 2V. If the VCC is less than the threshold voltage of 2V, none of the transistors can be turned on, and the circuit will not work. In fig. 5a shows a situation where the voltage of the power supply corresponds exactly to the threshold voltage. In this case, the circuit should work with 100% hysteresis. However, this is not entirely hysteresis, since both output transistors are closed, and the output voltage is maintained at the gate capacitors following the circuit circuit. If the VCC is within the limits of one and two threshold voltages (Fig. 5b), the “hysteresis” decreases, as the VCC approaches the value equivalent to 2VT (Fig. 5c). With a VCC voltage equivalent to two threshold voltages, there is no “hysteresis"; also there is no through current through two simultaneously open output transistors at the time of switching. When the VCC value exceeds two threshold voltages, the curves of the transfer characteristic begin to round out (Fig. 5d). When the VIN passes through the area where both transistors are open, i.e. in the conducting state, the currents flowing in the channels of the transistors create voltage drops that give rounding characteristics.

When considering a CMOS system for noise, it is necessary to consider at least two characteristics: noise immunity and noise immunity margin.

Modern CMOS circuits have a typical noise immunity value of 0.45VCC. This means that a false input signal of 0.45VCC or less than VCC or GND will not propagate in the system as an erroneous logic level. This does not mean that the output of the first circuit will not receive any signal at all. In fact, as a result of the influence of the interference signal, the output signal will appear at the output, but it will be attenuated in amplitude. As this signal propagates in the system, it will be weakened by subsequent circuits even more, until it completely disappears. Typically, such a signal does not change the output state of the logic element. In a normal trigger, a false input clock pulse with an amplitude of 0.45VCC will not lead to a change in its state.

The manufacturer of CMOS chips also guarantees a noise immunity margin of 1 Volt over the entire range of supply voltages and temperatures and for any combination of inputs. This is just a deviation of the noise immunity characteristic, for which a special set of input and output voltages is guaranteed. In other words, from this characteristic it follows that in order for the output signal of the circuit, expressed in Volts, to be within 0.1VCC of the value of the corresponding logic level (“zero” or “unity”), the input signal should not exceed the value 0, 1VCC plus 1 Volt above ground or below power. Graphically, this situation is shown in Fig. four.

These characteristics closely resemble the noise margin of standard TTL circuits, which is 0.4 V (Fig. 6). To complete the picture of the dependence of the output voltage VOUT on the input VIN, we present the curves of the transfer characteristics (Fig. 5).

SYSTEM APPLICATION ANALYSIS

In this section, various situations that arise during the development of the system are considered: unused inputs, parallel connection of elements to increase the load capacity, cabling of data buses, coordination with logical elements of other families.

UNUSED INPUTS

Simply put, unused inputs should not be left unconnected. Due to the very large input impedance (1012 Ohms), a floating input can drift between logical “zero” and “unity”, creating unpredictable behavior of the output circuit and the associated problems in the system. All unused inputs must be connected to a power bus, a “common” wire, or another used input. The choice is not accidental, since the possible influence on the output load capacity of the circuit should be taken into account. Consider, for example, the four-input element 4I-NOT, used as a two-input logic gate 2I-NOT. Its internal structure is shown in fig. 7. Let inputs A and B be unused inputs.

If unused inputs must be connected to a fixed logic level, then inputs A and B must be connected to the power bus to enable other inputs to work. This will turn on the lower A and B transistors and turn off the corresponding upper A and B. In this case, no more than two upper transistors can be turned on simultaneously. However, if inputs A and B are connected to input C, the input capacitance triples, but each time a logic “zero” level is applied to input C, the upper transistors A, B, and C turn on, tripling the value of the maximum output current of the logical “unit” level . If the logic level “zero” also arrives at input D, all four upper transistors are turned on. Thus, connecting unused inputs of an AND-NOT element to the power bus (OR NOT to a “common” wire) will turn them on, but connecting unused inputs to other used inputs guarantees an increase in the output leakage current of the logical “unit” level, in the case of an element AND-NOT (or output flowing current level of logical “zero”, in the case of the element OR-NOT).

For series-connected transistors, an increase in the output current does not occur. Given this circumstance, a multi-input logic element can be used to directly control a powerful load, for example, a relay coil or an incandescent lamp.

LOCALLY INCLUDED LOGIC ELEMENTS

Depending on the type of logic element, combining the inputs guarantees an increase in load capacity for leakage or leakage currents, but not two at the same time. In order to guarantee an increase in two output currents, several logic elements must be connected in parallel (Fig. 8). In this case, an increase in the load capacity is achieved due to the parallel connection of several chains of transistors (Fig. 7), thereby increasing the corresponding output current.

WIRING DATA BUS

There are two main ways to do this. The first method is the parallel connection of conventional CMOS buffer elements (for example,). And the second, most preferred, way is to connect the elements with three output states.

FILTRATION POWER SUPPLY INTERFERENCE

Since CMOS circuits can operate over a wide range of supply voltages (3-15 V), minimal filtering is required. The minimum voltage value of the power source is determined by the maximum operating frequency of the fastest element in the system (usually a very small part of the system operates at the maximum frequency). Filters should be selected on the basis of maintaining the supply voltage approximately in the middle between the indicated minimum value and the maximum voltage at which the microcircuits are still operational. However, if you want to minimize power dissipation, the voltage of the power source should be chosen as low as possible, while satisfying the performance requirements.

MINIMIZATION OF DISPENSED SYSTEM POWER

In order to minimize the power consumption of the system, it must operate at a minimum speed, performing the task with a minimum supply voltage. Instantaneous values \u200b\u200bof dynamic (AC) and static (DC) power consumption increase, both with increasing frequency and voltage of the power source. Dynamic Power Consumption (AC) is a function of the product CV2f. This is the power dissipated in the buffer element that controls the capacitive load.

It is obvious that the dynamic power consumption increases in direct proportion to the frequency and in proportion to the square of the voltage of the power source. It also increases with increasing load capacity, determined mainly by the system, and is not a variable. Static (DC) power consumption is dissipated during switching times and is the product of VI. In any CMOS element, instantaneous current arises from the power bus to the “common" wire (at VCC\u003e 2VT) fig. 9.

The maximum current amplitude is a rapidly increasing function of the input voltage, which, in turn, is a function of the voltage of the power source (Fig. 5d).
The actual value of the product of VI power dissipated by the system is determined by three indicators: the voltage of the power source, the frequency and times of the rise and fall edges of the input signal. A very important factor is the rise time of the input signal. If the rise time is long, the power dissipation increases, because the current path is set for the entire time until the input signal passes the region between the threshold voltages of the upper and lower transistors. Theoretically, if the rise time were assumed to be zero, the current path would not occur, and the VI power would be zero. However, since the rise time is of course small, a through current always appears, which rapidly increases with increasing supply voltage.

There is another circumstance regarding the rise time of the input signal and power consumption. If the circuit is used to control a large number of loads, the rise time of the output signal will increase. This will increase the VI power dissipation in each device controlled by such a circuit (but not in the control circuit itself). If the power consumption reaches a critical value, it is necessary to increase the steepness of the output signal by parallel switching on the buffer elements or by dividing the loads in order to reduce the total power consumption.

Now let’s summarize the effects of the effects of power supply voltage, input voltage, rise and fall times of the edges of the input signal, load capacitance on power dissipation. The following conclusions can be made:

Power supply voltage. The product CV2f of power dissipation increases in proportion to the square of the supply voltage. The product VI of the power dissipation increases approximately in proportion to the square of the voltage of the power source.
Input voltage level. The product VI of the power dissipation increases if the input voltage is between “zero potential (GND) plus threshold voltage” and “supply voltage (VCC) minus threshold voltage”. The highest power dissipation is observed when the VIN approaches 0.5 VCC. The input voltage level does not affect CV2f.
Rise time of the input signal. The product VI of the power dissipation increases with increasing rise time, since the through current through the simultaneously open output transistors is set for a longer time. The rise time of the input signal also does not affect the CV2f product.
Load capacity. The product CV2f of the power dissipated in the circuit increases in proportion to the load capacitance. The product VI of the power dissipation is independent of the load capacity. However, an increase in the load capacitance will lead to an increase in the rise times of the edges of the output signal, which, in turn, will lead to an increase in the product VI of the dissipated power in the logic elements controlled by this signal.

AGREEMENT WITH LOGIC ELEMENTS OF OTHER FAMILIES

There are two basic rules for matching elements of all other families with CMOS chips. Firstly, the CMOS circuit must provide the necessary requirements for input currents and voltages of elements of other families. And secondly, and even more importantly, the amplitude of the output signal of the logic elements of other families should maximally correspond to the voltage of the power source of the CMOS circuit.

P-CHANNEL MOS SCHEMES

There are a number of requirements that must be met when harmonizing P-MOS and CMOS circuits. Firstly, it is a set of power supplies with different voltages. Most P-MOS circuits are designed to operate at voltages from 17 V to 24 V, while CMOS circuits are designed for a maximum voltage of 15 V. Another problem with P-MOS circuits, unlike CMOS, is the significantly lower output amplitude signal than the voltage of the power source. The output voltage of the P-MOS circuitry varies from almost a more positive supply voltage potential (VSS) to several volts above a more negative potential (VDD). Therefore, even in the case of operation of the P-MOS circuit from a source voltage of 15 V, the amplitude of its output signal will still be less than necessary to ensure consistency with the CMOS circuit. There are several ways to solve this problem, depending on your system configuration. Consider two ways to build a system entirely on MOS schemes and one method when TTLS schemes are used in the system.

In the first example, only P-MOS and CMOS circuits with a supply voltage of less than 15 V are used (see Fig. 10). In this configuration, the CMOS circuit controls the P-MOS directly. However, the P-MOS circuit cannot control the CMOS directly, since its output voltage of the logic zero level significantly exceeds the zero potential of the system. To “pull” the output potential of the circuit to zero, an additional RPD resistor is introduced. Its value is chosen small enough to provide the desired RC time constant when switching the output from “unit” to “zero” and, at the same time, large enough to provide the necessary level of logical “unit” level. This method is also suitable for outputs of P-MOS circuits with open drains.

Another way in a fully MOS system is to use a reference voltage source based on a conventional zener diode to form a more negative potential supplying a CMOS circuit (Fig. 11).

In this configuration, the power supply of the P-MOS circuitry is used with a voltage of 17-24 V. The reference voltage is selected so as to reduce the supply voltage of the CMOS circuits to the minimum output voltage range of the P-MOS circuitry. The CMOS circuit can still drive the P-MOS directly, but now, the P-MOS circuit can control the CMOS without a pull-up resistor. Other limitations are: the supply voltage of the CMOS circuits, which should be less than 15 V, and the need to provide a reference source of sufficient current to power all CMOS circuits in the system. This solution is quite suitable if the power supply of the P-MOS circuit should be more than 15 V, and the current consumption of the CMOS circuits is small enough so that it can be provided by the simplest parametric stabilizer.

If the system uses TTLS circuits, then there must be at least two power sources. In this case, the CMOS circuit can operate from a unipolar source and control the P-MOS circuit directly (Fig. 12).

N-CHANNEL MOSFETS

Matching CMOS with N-MOS schemes is simpler, although some problems exist. Firstly, N-MOS circuits require a lower power supply voltage, usually in the range of 5-12 V. This allows them to be matched directly with CMOS circuits. Secondly, the amplitude of the output signal of the CMOS circuits is in the range from almost zero to the voltage of the power source minus 1-2 V.

At higher values \u200b\u200bof the voltage of the power source, N-MOS and CMOS circuits can work directly, since the output level of the logical unit of the N-MOS circuit will differ from the voltage of the power source by only 10-20%. However, at lower values \u200b\u200bof the supply voltage, the voltage of the level of the logical unit will be already 20-40% less, therefore, it is necessary to include a “pull-up” resistor (Fig. 13).

TTL-, TTLSH-SCHEMES

When matching these families with CMOS circuits, two questions arise. First, is there enough logical level voltage for the bipolar families to directly control CMOS circuits? TTL and TTLSh circuits are quite capable of controlling the CMOS circuits of the 74HCXX series directly without additional pull-up resistors. However, they are not able to control the CMOS circuits of the CD4000 series (K561, KR1561), since the characteristics of the latter do not guarantee operability in the case of direct connection without pull-up resistors.

TTLS circuits are capable of directly controlling CMOS circuits over the entire operating temperature range. Standard TTL circuits are capable of directly controlling CMOS circuits over most of the temperature range. However, closer to the lower boundary of the temperature range, the voltage level of the logical unit of the TTL circuits decreases and the introduction of a “pull-up” resistor is recommended (Fig. 14).

According to the dependence of allowable voltage values \u200b\u200bof input levels on the voltage of the power source for CMOS circuits (see Fig. 4), if the input voltage exceeds VCC-1.5 V (at VCC \u003d 5 V), then the output voltage will not exceed 0.5 V . The next CMOS element will amplify this voltage of 0.5 V to the corresponding voltage of VCC or GND. The logic level voltage “1” for standard TTL circuits is at least 2.4 V with an output current of 400 μA. This is the worst case, since the output voltage of the TTL circuit will only approach this value at minimum temperature, maximum input level “0” (0.8 V), maximum leakage currents and minimum supply voltage (VCC \u003d 4.5 V).

Under normal conditions (25 ° C, VIN \u003d 0.4 V, rated leakage currents in the CMOS circuit and the voltage of the power supply VCC \u003d 5 V), the logic level “1” will most likely correspond to VCC-2VD or VCC-1.2 V. If you change the temperature alone, the output voltage will change according to the dependence “two times -2 mV by one degree of temperature” or “-4 mV by degree”. The VCC-1.2 V voltage is enough to directly control the CMOS circuit without the need for a pull-up resistor.

If under certain conditions the output voltage of the TTL circuit of the logic level “1” can drop below VCC-1.5 V, it is necessary to use a resistor to control the CMOS circuit.
The second question is whether the CMOS circuit can provide sufficient output current to provide an input voltage level of logic “0” for the TTL circuit? For a logical “1” such a problem does not exist.

For the TTLS circuit, the input current is small enough to provide direct control of two such inputs. For a standard TTL circuit, the input current is ten times higher than the current of the TTL circuit and, therefore, the output voltage of the CMOS circuit, in this case, will exceed the maximum allowable voltage level of the logic “0” level (0.8 V). However, carefully studying the specification of the output load capacity of CMOS circuits, you can see that the two-input I-NOT element can control one TTL input, although in an extreme case. For example, the output voltage of the logic “zero” level for the MM74C00 and MM74C02 devices in the entire temperature range is 0.4 V at a current of 360 μA, with an input voltage of 4.0 V and a supply voltage of 4.75 V. Both circuits are shown in Fig. 15.

Both schemes have the same load capacity, but their structures are different. This means that each of the two lower transistors of the MM74C02 can provide the same current as the two MM74C00 transistors connected in series. Two transistors MM74C02 together can provide twice as much current at a given output voltage. If we allow the increase in the output voltage of the logical “zero” to a value of 0.8 V, then the MM74C02 can provide four times more output current than 360 μA, i.e. 1.44 mA, which is close to 1.6 mA. In fact, a current of 1.6 mA is the maximum input current for a TTL input, and most TTL circuits operate at a current of not more than 1 mA. Also, a current of 360 μA is the minimum output current for CMOS circuits. The real value is in the range of 360-540 μA (which corresponds to the input current of 2-3 TTLSh inputs). A current of 360 μA is indicated for an input voltage of 4 V. For an input voltage of 5 V, the output current will be of the order of 560 μA in the entire temperature range, making controlling the TTL input even easier. At room temperature and an input voltage of 5 V, the output of the CMOS circuit can provide a current of 800 μA. Therefore, the two-input OR-NOT element will provide an output current of 1.6 mA at a voltage of 0.4 V, if 5 V is supplied to both inputs of the OR-NOT element.

From this it can be concluded that one two-input OR-NOT element, which is part of the MM74C02, can be used to control a standard TTL input instead of a special buffer. However, this will lead to some decrease in noise immunity in the temperature range.

Information sources

Lecture. Processor manufacturing

Microprocessoris an integrated circuit formed on a small silicon crystal. Silicon is used in microcircuits due to the fact that it has semiconductor properties: its electrical conductivity is greater than that of dielectrics, but less than that of metals. Silicon can be made both an insulator that impedes the movement of electric charges, and a conductor - then electric charges will freely pass through it. The conductivity of a semiconductor can be controlled by introducing impurities.

Microprocessor contains millions of transistorsinterconnected by the thinnest conductors of aluminum or copper and used for data processing. This is how internal tires are formed. As a result, the microprocessor performs many functions - from mathematical and logical operations to controlling the operation of other microcircuits and the entire computer.

One of the main parameters of the microprocessor is the frequency of the chip, which determines the number of operations per unit of time, the frequency of the system bus, the amount of internal SRAM cache. According to the frequency of the chip, the processor is marked. The frequency of the crystal is determined by the frequency of switching transistors from closed to open. The ability of the transistor to switch faster is determined by the technology for producing silicon wafers from which the chips are made. The dimension of the process determines the size of the transistor (its thickness and gate length).

How do microchips

As you know from the school physics course, in modern electronics, the main components of integrated circuits are semiconductors p-type and n-type (depending on the type of conductivity). Semiconductor - this substance is superior in conductivity to dielectrics, but inferior to metals. The basis of both types of semiconductors can be silicon (Si), which in its pure form (the so-called intrinsic semiconductor) conducts electric current poorly, however, the addition (incorporation) of a certain impurity into silicon can radically change its conductive properties. There are two types of impurities: donor and acceptor.

Donor impurity leads to the formation of n-type semiconductors with electronic type of conductivity, and the acceptor one to the formation of p-type semiconductors with hole type conductivity. The contacts of p- and n-semiconductors allow the formation of transistors - the main structural elements of modern microcircuits. Such transistors, called CMOS transistors, can be in two main states: open when they conduct electric current, and locked - while they do not conduct electric current. Since CMOS transistors are the main elements of modern microcircuits, let's talk about them in more detail.

Speaking of Intel processors, they often use such specific concepts as the 0.13-micron process, and more recently, the 90-nanometer process. For example, it is customary to say that the new Intel Pentium 4 processor with Northwood core is made using 0.13-micron technology, and the future generation of processors will be based on a 90-nanometer process. What is the difference between these technological processes and how does it affect the capabilities of the processors themselves?

How is a CMOS transistor

The simplest n-type CMOS transistor has three electrodes: source, shutter and drain. The transistor itself is made in a p-type semiconductor with hole conductivity, and n-type semiconductors with electronic conductivity are formed in the drain and source regions. Naturally, due to the diffusion of holes from the p-region to the n-region and the back diffusion of electrons from the n-region to the p-region, depleted layers (layers in which there are no main charge carriers) are formed at the boundaries of the transitions of the p and n regions. In the normal state, that is, when no voltage is applied to the gate, the transistor is in a “locked” state, that is, it is not able to conduct current from source to drain. The situation does not change, even if the voltage between the drain and the source is applied (in this case, we do not take into account leakage currents caused by the motion of minority charge carriers, that is, holes for the n-region and electrons for the p-region, under the influence of generated electric fields).

However, if positive potential is applied to the shutter (Fig. 1), the situation will radically change.

Fig. 1. The principle of operation of the CMOS transistor

Under the influence of the gate electric field, the holes are pushed deep into the p-semiconductor, and the electrons, on the contrary, are pulled into the region under the gate, forming a channel enriched with electrons between the source and the drain. If a positive voltage is applied to the gate, these electrons begin to move from the source to the drain. In this case, the transistor conducts current - they say that the transistor "opens". If the voltage is removed from the gate, the electrons cease to be drawn into the region between the source and the drain, the conductive channel is destroyed and the transistor ceases to pass current, that is, it is “locked”. Thus, by changing the voltage at the gate, you can open or close the transistor, similar to how you can turn on or off a conventional toggle switch, controlling the passage of current through the circuit. That is why transistors are sometimes called electronic switches. However, unlike conventional mechanical switches, CMOS transistors are virtually inertia-free and able to switch trillions of times per second from open to locked state! It is this characteristic, that is, the ability to instantly switch, that ultimately determines the speed of the processor, which consists of tens of millions of such simple transistors.

So, a modern integrated circuit consists of tens of millions of simple CMOS transistors.

Here is a cross-sectional image of the processor:

There is a protective metal cover on top, which, in addition to the protective function, also acts as a heat distributor - it is it that we generously smear with thermal grease when we install the cooler. Under the heat distributor is the very piece of silicon that performs all user tasks. Even lower is a special substrate, which is needed for wiring contacts (and increasing the area of \u200b\u200bthe "legs") so that the processor can be installed in the socket of the motherboard.

The chip itself consists of silicon, on which there are up to 9 layers of metallization (made of copper) - just as many levels are needed that, according to a certain law, it is possible to connect transistors located on the silicon surface (since it is simply impossible to do all this at the same level). In fact, these layers act as connecting wires, only on a much smaller scale; so that the "wires" do not short-circuit each other, they are separated by a layer of oxide (with a low dielectric constant).