Lecture. Processor manufacturing
Microprocessoris an integrated circuit formed on a small silicon crystal. Silicon is used in microcircuits due to the fact that it has semiconducting properties: its electrical conductivity is higher than that of dielectrics, but less than that of metals. Silicon can be made both as an insulator that prevents the movement of electric charges, and as a conductor - then electric charges will pass freely through it. The conductivity of a semiconductor can be controlled by introducing impurities.
Microprocessor contains millions of transistorsconnected to each other by the thinnest conductors of aluminum or copper and used for data processing. This is how the internal tires are formed. As a result, the microprocessor performs many functions - from mathematical and logical operations to controlling the operation of other microcircuits and the entire computer.
One of the main parameters of a microprocessor is the frequency of the crystal, which determines the number of operations per unit of time, the frequency of operation system bus, the amount of internal SRAM cache. The processor is marked by the frequency of the crystal. The frequency of the crystal is determined by the switching frequency of the transistors from the closed state to the open state. The ability of a transistor to switch faster is determined by the technology used to manufacture the silicon wafers from which the chips are made. The dimension of the technological process determines the size of the transistor (its thickness and gate length).
How microcircuits are made
As you know from the school physics course, in modern electronics, the main components integrated circuits are semiconductors p-type and n-type (depending on the type of conductivity). Semiconductor is a substance that surpasses dielectrics in conductivity, but is inferior to metals. Both types of semiconductors are based on silicon (Si), which in its pure form (the so-called intrinsic semiconductor) does not conduct well electricity, however, the addition (incorporation) of a certain impurity into silicon makes it possible to radically change its conducting properties. There are two types of mixins: donor and acceptor.
Donor admixture leads to the formation of n-type semiconductors with electronic type of conductivity, and the acceptor - to the formation of p-type semiconductors with hole type of conductivity. Contacts of p- and n-semiconductors allow you to form transistors - the main structural elements modern microcircuits. Such transistors, called CMOS transistors, can be in two basic states: open, when they conduct electric current, and closed, when they do not conduct electric current. Since CMOS transistors are the main elements of modern microcircuits, let's talk about them in more detail.
When talking about Intel processors, they often use such specific concepts as 0.13-micron technological process, and in recent times - 90 nanometer technological process. For example, it is customary to say that new intel processor Pentium 4 with Northwood core is made using 0.13-micron technology, and the next generation of processors will be based on 90-nanometer technological process. What is the difference between these technological processes and how does it affect the capabilities of the processors themselves?
How a CMOS transistor works
The simplest n-type CMOS transistor has three electrodes: source, gate and drain... The transistor itself is made in a p-type semiconductor with hole conductivity, and n-type semiconductors with electronic conductivity are formed in the drain and source regions. Naturally, due to the diffusion of holes from the p-region to the n-region and the reverse diffusion of electrons from the n-region to the p-region, depleted layers (layers in which the majority charge carriers are absent) are formed at the boundaries of the transitions of the p- and n-regions. In the normal state, that is, when no voltage is applied to the gate, the transistor is in a "locked" state, that is, it is not able to conduct current from the source to the drain. The situation does not change even if we apply a voltage between the drain and the source (in this case, we do not take into account the leakage currents caused by the movement under the influence of the generated electric fields of minority charge carriers, that is, holes for the n-region and electrons for the p-region).
However, if a positive potential is applied to the gate (Fig. 1), then the situation will change radically.
Figure: 1. The principle of operation of a CMOS transistor
Under the influence of the electric field of the gate, holes are pushed deep into the p-semiconductor, and electrons, on the contrary, are drawn into the region under the gate, forming an electron-enriched channel between the source and drain. If a positive voltage is applied to the gate, these electrons begin to move from source to drain. In this case, the transistor conducts current - they say that the transistor "opens". If the voltage is removed from the gate, electrons stop being drawn into the region between the source and drain, the conducting channel is destroyed and the transistor stops passing current, that is, it is "locked". Thus, by changing the voltage at the gate, you can open or turn off the transistor, in the same way as you can turn on or off a conventional toggle switch by controlling the passage of current through the circuit. This is why transistors are sometimes called electronic switches. However, unlike conventional mechanical switchesCMOS transistors are virtually inertia-free and are capable of going from open to locked state trillions of times per second! It is this characteristic, that is, the ability of instantaneous switching, that ultimately determines the speed of the processor, which consists of tens of millions of such simplest transistors.
So, a modern integrated circuit consists of tens of millions of the simplest CMOS transistors.
Here is a picture cross section processor:
Above there is a protective metal cover, which, in addition to a protective function, also acts as a heat spreader - it is this that we liberally smear with thermal paste when we install the cooler. Under the heat spreader is the same piece of silicon that performs all the user's tasks. Even lower is a special substrate, which is needed for pinout (and increasing the area of \u200b\u200bthe "legs") so that the processor can be installed in a motherboard socket.
The chip itself consists of silicon, on which there are up to 9 metallization layers (made of copper) - this is exactly the number of levels needed so that, according to a certain law, it would be possible to connect transistors located on the silicon surface (since it is simply impossible to do all this at the same level). Basically, these layers act as connecting wires, only on a much smaller scale; so that the "wires" do not short each other, they are separated by a layer of oxide (with a low dielectric constant).
Let us dwell in more detail on the process of manufacturing microcircuits, the first stage of which is the production of silicon substrates.
Step 1. Growing blanks
Step 2. Application protective film dielectric (SiO2)
Step 3. Applying the photoresist
Step 4. Lithography
Step 5. Etching
Step 6. Diffusion (ion implantation)
Step 7. Spraying and deposition
Step 8. Final stage
Advanced technologies
The basis of CMOS elements is an inverter built on two complementary (complementary) MOS transistors ( n-MOS and p-MOS) with an isolated gate and an induced channel. A feature of this scheme ( fig. 4.17) is that the input voltage controls not only the key, but also the load transistor.
On fig. 4.5.2.the drain-gate characteristics of the used transistors are given. Transistor with n-channel ( VТ n) begins to conduct current if a positive voltage is applied to its gate, and a transistor with r-channel ( VT p) - if a negative voltage is applied to its gate with respect to the source.
It is important that both transistors have a "heel" in their drain-gate characteristics. Thus, if we want the circuit to work with a positive supply voltage (+ E P), then as a key transistor it is necessary to use VТ n, and as a load - VT p.
Figure: 4.17.1. CMOS inverter
Figure: 4.5.2. Gate characteristics of CMOS transistors
Inverter ( fig. 4.17) is constructed so that the source VT p is connected to E n,and the source VТ n - with the ground. Shutters VТ nand VT p are combined and serve as an input to the inverter, drains VТ nand VT p are also combined and serve as the output of the inverter. With this inclusion, the following formulas for determining the gate-source voltage will be valid VТ nand VT p: U zip \u003d U in, U zir \u003d U in -E p
U zip - gate-source voltage n-channel transistor ( VТ n);
U zir- gate-source voltage r-channel transistor ( VT p).
When considering the operation of the inverter, we will assume that VТ nand VT p have identical characteristics and the threshold voltage U Пп \u003d½ U Pr½ \u003d 1.5V.
U pp- threshold voltage n-channel transistor;
U Pr- threshold voltage p-channel transistor.
Consider the operation of a CMOS inverter according to its HVV ( fig. 4.18-a), on which four sections and dependencies can be distinguished U ZI = f(U BX) (fig. 4.18-b).
Section 1: U 0 in £ U Пп... Wherein U zip \u003d U in and VТ n closed, U zir \u003d U in - E p< U Prand VT p open.
Figure: 4.18. CMOS inverter specifications:
a) HVB, b) U SHUTTER-SOURCE \u003d f (U IN); c) I POTR \u003d f (U BX)
VТ nclosed), VT p is in deep saturation, the output will be a voltage close to E P ( U 1 OUT » E P).
Section II: U П\u003e U ВХ\u003e U Пп,
where U P - voltage at which the circuit switches
and U OUT \u003d 0.5 (U 1 - U 0). U SPTA \u003d U IN\u003e U Ppand VТ nstarts to open, U ЗИР \u003d U ВХ -Е П< U Пр and VT p is open.
On this site ½ U SPTA½ < ½ U ZIR½, therefore VT p will remain saturated and VТ n - in active mode.
VТ n.
The current flowing in the circuit creates a voltage drop across the channel VT p, due to this, the output voltage begins to decrease. However, with an increase in the input voltage in this section, the output voltage decreases slightly, since VT p is still saturated.
Dot U p: U VX \u003d U P \u003d 0.5E P;
U SPTA \u003d U IN \u003d U P\u003e U Ppand VТ n open; 0.5E P< U Пр and VT p is open.
At this point | U SPTA|=|U ZIR| therefore, the resistances of the channels of both transistors are also equal. Thus, the output will be a voltage equal to half the voltage of the power supply ( U OUT=0,5E P). This point corresponds to the vertical section on the characteristic. At this point, the circuit draws maximum current, since both transistors are on. At the slightest change in the input voltage, the output voltage changes dramatically.
Section III: E P -½ U Pr½ \u003e U IN\u003e U P; U SPTA= U IN\u003e U Pp and VТ nopen; U ЗИР \u003d U ВХ -Е П< U Пр and VT P is open, but with growth U BX is becoming less and less open.
On this site U SPTA\u003e|U ZIR|, and therefore VТ nis in saturation, a VT p - in active mode.
The current consumed by the circuit is determined in this case by the transistor VT p.
The output voltage in this section is equal to the voltage drop on the channel VТ n... As VТ nis in saturation, then this drop is small, and with an increase U BX it decreases more and more.
Section IV: E p\u003e U in\u003e E p -½ U Pr½; U zip= U in\u003e U Pp and V nopen; U zir \u003d U in -E n\u003e U zipand VT p is closed.
In this state, the circuit practically does not consume current (since VT p is closed). VТ nis in deep saturation, while the output will have a voltage close to zero ( U out» 0).
As can be seen from HVB ( fig 4.5.1a), CMOS elements have good noise immunity. Noise immunity is equal to zero and one. This is because the switching point ( U in \u003d U P) lies exactly in the center of the input voltage range ( E P\u003e U in\u003e0). When E P \u003d + 5V maximum value interference can reach 1.5V. With growth E P the absolute noise immunity is increased. The immunity of CMOS elements is approximately 30% of E P (U 0 in max"0.3 E P, U 1 in.min"0.7 E P).
Since the input of the CMOS inverter is MOS transistors with an insulated gate, the input impedance is very high (10 12 ¸ 10 13 Ohm). Therefore, such circuits practically do not consume current at the input.
The output impedance of CMOS circuits is small as in the Log state. 0 and in the Log state. 1, since one of the transistors VТ n or VT p will definitely be open. Thus, the output resistance is determined by the channel resistance of the open MOS transistor and amounts to 10 2 ¸10 3 Ohm.
High input impedance and low output impedance result in a high static branching ratio at the output. The branching factor will be limited from above only by the speed requirements. Since each input of the circuit has a certain capacity, then with an increase in the branching ratio, the load capacity will increase, which, in turn, will increase the switching time of the element.
Thus, as the operating frequency decreases, the branching ratio will increase. In connection with the above, it is clear that the input and load characteristics lose their meaning. The load characteristic is only important when coupling CMOS elements with elements of other types.
The low output impedance of the element in both states allows the load capacitance to be quickly recharged. This results in fast turn-on and turn-off delays. In practice, the delay times are 50 ¸ 200 ns.
Figure: 4.5.1c explains the process of current consumption by the circuit.
In a static position, CMOS circuits consume very little current (10 -6 -10 -7 A).
Basically, current is consumed when switching a circuit, while U SPTAand ½ U ZIR½> U POR and both transistors VТ n and VT p open (sections II and III on CVB) However, the value of this current is less than that of TTL circuits, since the volume resistances of open MOS transistors exceed the resistances of open bipolar transistors. For this reason, there is no clipping resistor in CMOS circuits.
When switching the circuit, current is also consumed to charge the load capacitance. The magnitude of this current can be defined as I \u003d CEf П Where f P Is the switching frequency of the circuit.
The advantages of CMOS circuits also include the ability to operate at different supply voltages (3-15V). With an increase in the supply voltage, the absolute noise immunity will increase, however, the current consumption will also increase (sections II and III on the CVB will become wider). With a supply voltage of + 5V, the signal levels of the CMOS circuits become compatible with the TTL levels.However, care must be taken to U 1 I / min for CMOS would be more E P - |U OL | for secure locking VT p... For this purpose, the TTL output is often connected through a resistor to E P.
The operation of CMOS circuits on TTL circuits is carried out, as a rule, through wiring diagrams.
On fig. 4.19the diagram of the basic element of the CMOS type is shown. The element implements the 4I-NOT function. The transistors are positioned in such a way that no through current will flow in the circuit for any combination of input signals. Elements of the OR-NOT type are constructed in a similar way. (fig.4.20).
In such circuits, due to the series connection of transistors in one of the arms, the output resistance increases in one of the states. Therefore, such elements have different on and off times. For the NAND element, the on time is longer than the off time, and for the NOR element, vice versa.
Figure: 4.19. Implementation of 4I-NOT function on CMOS
Figure: 4.20. Implementation of 4OR-NOT function on CMOS
Due to the very high input impedance, even a static charge can create a breakdown voltage. To protect against high-voltage charges of static electricity, there is a special protection circuit at the inputs of CMOS circuits (inside the microcircuit) (fig.4.21).
Figure: 4.21. CMOS Inverter with ESD Gate Protection
Diodes VD1, VD2 and VD3 protect the gate insulation from breakdown. Diodes VD4 and VD7 protect the inverter output from breakdown between r and n areas. Diodes VD5 and VD6 connected in series between the power rails to protect against accidental power polarity reversal.
Typical representatives of CMOS circuits are elements of the K564 series, which are characterized by the following parameters:
E P\u003d 3¸15V; U 0\u003d 0.01V (at E P\u003d 5V and I n=0); U 1\u003d 4.99V (at E P\u003d 5V and I n=0); I 0 in\u003d 0.2μA; I 1 in\u003d 0.2μA; I P\u003d 0.17mA (at E P\u003d 10V, F\u003d 100kHz and C n\u003d 50pF); t s\u003d 80ns; I 0 out\u003d 0.9mA (at U 0 out\u003d 0.5V and E P\u003d 10V); I 1 out\u003d 0.9mA (at U 1 out=E P-0.5V and E P\u003d 10V); C n \u003d200pF; With in\u003d 12pF.
An individual experiment (UIRS) requires special attention in preparation.
A prime example of how complex and confusing it is in prioritizing research and development projects is CMOS chips and their introduction to the market.
The fact is that the field effect that underlies the MOS structure was discovered back in the late 1920s, but radio engineering was then experiencing a boom in vacuum devices (radio tubes) and the effects found in crystal structures were considered unpromising.
Then, in the 40s, the bipolar transistor was practically reopened, and only then, when further research and improvement of bipolar transistors showed that this direction was leading to a dead end, scientists remembered the field effect.
This is how the MOS transistor appeared, and later the CMOS microcircuits. Letter TO at the beginning of the abbreviation means complementary, that is, complementary. In practice, this means that microcircuits use pairs of transistors with exactly the same parameters, but one transistor has an n-type gate, and the other transistor has a p-type gate. In a foreign manner, CMOS microcircuits are called CMOS (Complementary Metal-Oxide Semiconductor). The abbreviations KMDP, K-MOP are also used.
Among conventional transistors, an example of a complementary pair is the KT315 and KT361 transistors.
First, the K176 series based on field-effect transistors appeared on the market of electronic components, and, as a further development of this series, the K561 series, which has become very popular, was developed. This series includes a large number of logic chips.
Because the field effect transistors are not as critical to the supply voltage as bipolar ones, this series is powered by a voltage from +3 to + 15V. This allows this series to be widely used in different devices, including battery powered. In addition, devices assembled on K561 series microcircuits consume very little current. And no wonder, because the basis of CMOS microcircuits is a field-effect MOS transistor.
For example, the K561TP2 microcircuit contains four RS flip-flops and consumes a current of 0.14 mA, and a similar microcircuit of the K155 series consumed at least 10 - 12 mA. Microcircuits based on CMOS structures have a very high input impedance, which can reach 100 megohms or more, so their load capacity is quite large. To the output of one microcircuit, you can connect the inputs of 10 - 30 microcircuits. For TTL microcircuits, such a load would cause overheating and failure.
Therefore, the design of nodes on microcircuits using CMOS transistors makes it possible to use simpler circuit solutions than when using TTL microcircuits.
Abroad, the most common analogue of the K561 series is labeled as CD4000. For example, the K561LA7 microcircuit corresponds to the foreign CD4011.
Using microcircuits of the K561 series, one should not forget about some of the nuances of their operation. It should be remembered that although the microcircuits are operational in a wide voltage range, when the supply voltage decreases, noise immunity drops, and the pulse "spreads out" slightly. That is, the closer the supply voltage is to the maximum, the steeper the pulse edges.
The figure shows a classic base element (gate) that inverts the input signal (NOT element). That is, if a logical unit comes to the input, then a logical zero is removed from the output and vice versa. A complementary pair of "n" and "p" gate type transistors is clearly shown here.
The following figure shows the basic element 2I - NOT. It is clearly seen that the resistors that are present in a similar element of the TTL microcircuit are absent here. From two such elements it is easy to get a trigger, and from a sequential series of triggers a direct road to counters, registers and storage devices.
With all the positive qualities of the K561 series integrated circuits, they, of course, have drawbacks. First, in terms of the maximum operating frequency, CMOS microcircuits are noticeably inferior to microcircuits with different logic and operating on bipolar transistors.
The frequency at which the K561 series works with confidence does not exceed 1 MHz. To coordinate microcircuits based on MOS structures with other series, for example, TTL, level converters K561PU4, K561LN2 and others are used. These microcircuits also synchronize the speed, which may differ from series to series.
But the biggest drawback of microcircuits on complementary MOS structures is the strongest sensitivity of the microcircuit to static electricity. Therefore, factories and laboratories are equipped with special jobs. On the table, all work is performed on a metal sheet, which is connected to a common ground bus. Both the soldering iron body and the metal bracelet worn on the worker's hand are connected to this bus.
Some microcircuits go on sale packed in foil, which short-circuits all the leads to each other. When working at home, it is also necessary to find a way for the static charge to drain at least onto the heating pipe. During installation, the power leads are soldered first, and only then all the rest.
Logic CMOS (CMDP) inverters
Chips on complementary MOS transistors (CMOS chips) are built on the basis of MOS transistors with n- and p-channels. The same input potential turns on the n-channel transistor and turns off the p-channel transistor. When a logical unit is formed, the upper transistor is open, and the lower one is closed. As a result, no current flows through the CMOS circuit. When a logical zero is formed, the lower transistor is open, and the upper one is closed. And in this case, the current from the power supply does not flow through the microcircuit. The simplest logic element is an inverter. an inverter made on complementary MOS transistors is shown in Figure 1.
Figure 1. Schematic diagram of an inverter made on complementary MOS transistors (CMOS inverter)
As a result of this feature of CMOS microcircuits, they have an advantage over the previously considered types - they consume current depending on the input clock frequency... An approximate graph of the dependence of the current consumption of a CMOS microcircuit, depending on the frequency of its switching, is shown in Figure 2
Figure 2. Dependence of the current consumption of a CMOS microcircuit on the frequency
Logic CMOS (CMDP) elements "AND"
Scheme logical element "AND-NOT" on CMOS chips almost coincides with the simplified AND circuit on electronically controlled keys that we looked at earlier. The difference lies in the fact that the load is connected not to the common wire of the circuit, but to the power source. The schematic diagram of the logic element "2I-NOT", made on complementary MOS transistors (CMOS), is shown in Figure 3.
Figure 3. Schematic diagram of the logic element "2I-NOT", made on complementary MOS transistors (CMOS)
In this circuit, an ordinary one could be used in the upper arm, however, when a low signal level is formed, the circuit would constantly consume current. Instead, p-MOS transistors are used as the load. These transistors form a resistive load. If a high potential is required at the output, then the transistors open, and if it is low, then they close.
In the circuit of the CMOS logic element "AND" shown in Figure 2, the current from the power supply to the output of the CMOS microcircuit will flow through one of the transistors if at least one of the inputs (or both at once) has a low potential (the logic level zero). If at both inputs of the logical CMOS element "AND" there is a level of logical unity, then both p-MOS transistors will be closed and a low potential will form at the output of the CMOS microcircuit. In this circuit, as well as in the circuit shown in Figure 1, if the transistors of the upper arm are open, then the transistors of the lower arm will be closed, therefore, in a static state, the current will not be consumed by the CMOS microcircuit from the power supply.
Conventional graphic representation of the CMOS logic element "2I-NOT" is shown in Figure 4, and the truth table is shown in Table 1. In Table 1, the inputs are designated as x 1 and x 2, and the output is F.
Figure 4. Conditional graphic representation of the logical element "2I-NOT"
Table 1. Truth table of a CMOS microcircuit performing "2I-NOT"
| x1 | x2 | F |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Figure 5. Schematic diagram of the logical element "OR-NOT", made on complementary MOS transistors
The CMOS 2OR-NOT gate uses series-connected p-MOS transistors as a load. In it, the current from the power source to the output of the CMOS microcircuit will flow only if all the transistors in the upper arm are open, i.e. if a low potential () is present at all inputs at once. If at least one of the inputs has a logic-one level, then the upper arm of the push-pull stage, assembled on CMOS transistors, will be closed and the current from the power supply will not flow to the output of the CMOS microcircuit.
The truth table of the logical element "2OR-NOT", implemented by the CMOS microcircuit, is shown in Table 2, and the conventional-graphic designation of these elements is shown in Figure 6.
Figure 6. "2OR-NOT" element
Table 2. Truth table of the MOS microcircuit performing the logical function "2 OR-NOT"
| x1 | x2 | F |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
At present, it is CMOS microcircuits that have received the greatest development. Moreover, there is a constant trend towards a decrease in the supply voltage of these microcircuits. The first series of CMOS microcircuits, such as K1561 (foreign analogue of C4000V), had a fairly wide range of supply voltage variation (3..18V). At the same time, when the supply voltage for a particular microcircuit decreases, its maximum operating frequency decreases. Later, as the production technology improved, improved CMOS microcircuits with better frequency properties and lower supply voltage appeared, for example, SN74HC.
Features of the use of CMOS microcircuits
The first and main feature of CMOS microcircuits is the high input impedance of these microcircuits. As a result, any voltage can be induced at its input, including equal to half the supply voltage, and stored on it for a long time. When half the power supply is applied to the input of the CMOS element, transistors in both the upper and lower arms of the output stage open, as a result, the microcircuit begins to consume an unacceptably large current and may fail. Conclusion: the inputs of digital CMOS microcircuits must never be left unconnected!
The second feature of CMOS chips is that they can operate when the power is off. However, they often work incorrectly. This feature is related to the design of the input stage. The complete schematic diagram of the CMOS inverter is shown in Figure 7.
Figure 7. Complete schematic diagram of a CMOS inverter
Diodes VD1 and VD2 were introduced to protect the input stage from static breakdown. At the same time, when a high potential is applied to the input of the CMOS microcircuit, it will go through the VD1 diode to the microcircuit power bus, and since it consumes a fairly small current, the CMOS microcircuit will start working. However, in some cases, this current may not be enough to power the microcircuits. As a result, the CMOS chip may not work properly. Conclusion: if the CMOS microcircuit does not work properly, carefully check the microcircuit power supply, especially the case leads. With a poorly soldered negative power output, its potential will differ from the potential of the common wire of the circuit.
The fourth feature of CMOS microcircuits - is the flow of impulse current through the power circuit when it switches from zero to single and vice versa. As a result, when switching from TTL microcircuits to CMOS analog microcircuits, the level of noise increases sharply. In some cases, this is important, and you have to abandon the use of CMOS microcircuits in favor of BICMOS or microcircuits.
Logic levels of CMOS chips
The logic levels of CMOS chips differ significantly from. In the absence of load current, the voltage at the output of the CMOS microcircuit coincides with the supply voltage (logic level of one) or with the potential of the common wire (logic level of zero). With an increase in the load current, the voltage of the logical unit can decrease to 2.8V (U p \u003d 15V) from the supply voltage. Allowable output voltage level digital CMOS microcircuits (series of microcircuits K561) with a five-volt power supply is shown in Figure 8.
Figure 8. Levels of logical signals at the output of digital CMOS microcircuits
As mentioned earlier, the voltage at the input of a digital microcircuit is usually allowed within a wide range compared to the output. For CMOS microcircuits agreed on a 30% stock. The boundaries of the logical zero and one levels for CMOS microcircuits with a five-volt power supply are shown in Figure 9.
Figure 9. Levels of logical signals at the input of digital CMOS microcircuits
When the supply voltage decreases, the boundaries of logical zero and logical unity can be determined in the same way (divide the supply voltage by 3).
CMOS families
The first CMOS microcircuits did not have protective diodes at the input, so their installation was very difficult. This is a family of K172 series microcircuits. The next improved family of CMOS chips of the K176 series received these protection diodes. It is quite widespread today. The K1561 series completes the development of the first generation of CMOS chips. In this family, a speed of 90 ns and a supply voltage range of 3 ... 15V were achieved. Since foreign equipment is currently common, I will give a foreign analogue of these CMOS microcircuits - C4000V.
A further development of CMOS microcircuits was the SN74HC series. These microcircuits have no domestic counterpart. They have a speed of 27 ns and can operate in the voltage range of 2 ... 6 V. They coincide in pinout and functional range with, but are not compatible with them in logical levelsTherefore, at the same time, CMOS microcircuits of the SN74HCT series (domestic analogue - K1564) were developed, compatible with TTL microcircuits and at logic levels.
At this time, there was a transition to a three-volt power supply. For it, SN74ALVC CMOS microcircuits were developed with a signal delay time of 5.5 ns and a supply range of 1.65 ... 3.6 V. These microcircuits are also capable of operating with a 2.5 volt supply. In this case, the signal delay time increases to 9 ns.
The most promising family of CMOS microcircuits is currently considered to be the SN74AUC family with a signal delay time of 1.9 ns and a power supply range of 0.8 ... 2.7 V.
CMOS logic gates
Equivalent circuit diagrams above can be obtained using only PMOS transistors. However, the most interesting is the combined use of PMOS and NMOS transistors. This technology is the most popular today and is called CMOS technology. It provides maximum cell performance with low power consumption compared to all other technologies.
In NMOS circuits, logic functions are implemented by a combination of NMOS transistor connections combined with a current-limiting element.
Because all elements built on NMOS transistors implement negative functions (NOT, OR-NOT, AND-NOT), then they can be conventionally represented as shown in the block diagram of Figure 1.9.
Figure 1.9 - The structure of the NMOS circuit
In this case, all transistor circuits are combined into a PDN (Pull-down Network) block - a negative logic block. For the implementation of direct logical functions, it is necessary to connect two negative elements, which reduces the speed of the entire element as a whole. The concept of CMOS circuits is based on the implementation of direct functions (AND, OR) on PMOS transistors in such a way that blocks of direct logic (PUN - Pull-up Network) and blocks of negative logic (PDN - Pull-down Network) are complements of each other. Then the logical circuit that implements a typical logical element will have the form shown in Figure 1.10.
Figure 1.10 - The structure of the CMOS circuit
For any combination of inputs, PDN sets the V f output to a logic-zero level, or PUN sets this output to a logic-high level. PDN and PUN have an equal number of transistors, which are placed so that the two units operate in parallel. Where PDN includes NMOS transistors connected in series, PUN is built on PMOS transistors connected in parallel and vice versa.
The simplest example of a CMOS circuit is an inverter, shown in Figure 1.11.
Figure 1.11 - Implementation of the CMOS inverter
When V x \u003d 0V, T2 is off and T1 is on. Therefore, V f \u003d 5V, and since T2 is off, no current flows through the transistors. When V x \u003d 5V, then T2 is open and T1 is closed. Thus, V f \u003d 0V, and there will still be no current in the circuit, because transistor T1 is off. This property is true for all CMOS circuits - logic gates practically do not consume current in a static mode. The current in such circuits will flow only during the switching of elements (that's why, with an increase in the frequency of operation of devices built using this technology, energy consumption also increases). Consequently, CMOS circuits have become the most popular technology for digital logic devices.
Figure 1.12 represents the principal electrical circuit logical element NAND CMOS. The implementation of this element is similar to the NMOS circuit shown in Figure 1.5, except that the current limiting resistor has been replaced by a PUN block consisting of two PMOS transistors connected in parallel. The truth table in the figure shows the state of each of the four transistors for each logical combination of inputs x 1 and x 2. It is easy to check that this scheme implements the logical function NAND. In a static state, there is no path for current flow from V DD to Gnd.
Figure 1.12 - CMOS-implementation of the logical element NAND
The circuit in Figure 1.12 can be obtained from a logical expression that defines a logical NAND function,. This expression defines the conditions in which f \u003d 1; therefore, it determines the behavior of the PUN block. Since this block consists of PMOS transistors, which open when a logic zero is applied to their inputs, the input variable x i turns on the transistor if x i \u003d 0. According to de Morgan's rule, we have:
In this way f \u003d 1when either input x 1 or input x 2 is logic zero, which means the PUN must have two PMOS transistors connected in parallel. The PDN block must complement the function f, which is:
f \u003d x 1 x 2
Function f \u003d 1when both inputs x 1 and x 2 are 1, so the PDN unit must have two NMOS transistors in series.
The circuit for the CMOS implementation of the OR-NOT element can be obtained from a logical expression.
