Logic levels of CMOS microcircuits. Comparison of the main characteristics of TTL and CMOP microcircuits

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Digital microcircuits. Logic types, enclosures

Well, first let's say this: microcircuits are divided into two large types: analog and digital. Analog microcircuits work with an analog signal, and digital ones, respectively, with a digital one. We will talk specifically about digital microcircuits.

More precisely, even, we will not talk about microcircuits, but about elements of digital technology that can be "hidden" inside the microcircuit.

What are these elements?

Some of the names you have heard, some, maybe not. But believe me, these names can be pronounced aloud in any cultural society - these are absolutely decent words. So, a rough list of what we will be studying:

• Triggers
• Counters
• Scramblers
• Decoders
• Multiplexers
• Comparators

All digital microcircuits work with digital signals. What it is?

Digital signals - these are signals that have two stable levels - a logical zero level and a logical one level. For microcircuits made using different technologies, the logic levels may differ from each other.

Currently, two technologies are most widely used: TTL and CMOS.

TTL - Transistor-Transistor Logic;
CMOS - Complimentary Metal-Oxide-Semiconductor.

For TTL, the zero level is 0.4 V, the unity level is 2.4 V.
For CMOS logic, the zero level is very close to zero volts, the one level is approximately equal to the supply voltage.

In every way, one - when the voltage is high, zero - when it is low.

BUT! Zero voltage at the output of the microcircuit does not mean that the output is "dangling in the air." In fact, it is just connected to ground. Therefore, several logical conclusions cannot be connected directly: if there are different levels on them, a short circuit will occur.

In addition to differences in signal levels, the types of logic also differ in terms of power consumption, speed (frequency limit), load capacity, etc.

The type of logic can be recognized by the name of the microcircuit. More precisely - by the first letters of the name, which indicate to which series the microcircuit belongs. Within any series, there may be microcircuits produced using only one technology. To make it easier for you to navigate, here is a small pivot table:

	TTL	TTLSh	CMOS	Bastard action. CMOS	ESL
Explanation of the name	Transistor-Transistor Logic	TTL with Schottky diode	Complimentary Metal Oxide Semiconductor		Emitter-Consistent Logic
Basic series microcircuits	K155 K131	K555 K531 KR1533	K561 K176	KR1554 KR1564	K500 KR1500
Series of bourgeois microcircuits	74	74LS 74ALS	CD40 H 4000	74AC 74 HC	MC10 F100
Propagation delay, nS	10…30	4…20	15…50	3,5..5	0,5…2
Max. frequency, MHz	15	50..70	1…5	50…150	300…500
Supply voltage, V	5 ± 0.5	5 ± 0.5	3...15	2...6	-5.2 ± 0.5
Consumption current (no load), mA	20	4...40	0,002...0,1	0,002...0,1	0,4
Log level 0, V	0,4	0,5	< 0,1	< 0,1	-1,65
Log level. 1, B	2,4	2,7	~ U pit	~ U pit	-0,96
Max. output current, mA	16	20	0,5	75	40

The most common today are the following series (and their imported counterparts):

• TTLSh - K555, K1533
• CMOS - KR561, KR1554, KR1564
• ESL - K1500

The type of logic is chosen mainly based on the following considerations:

Speed \u200b\u200b(operating frequency)
- Energy consumption
- cost

But there are situations where one type cannot be enough. For example, one unit must be low power and the other high speed. Chips of CMOS technology have low consumption. High speed - ESL.

In this case, you will need to install level converters.

True, some types can be matched well without converters. For example, a signal from the output of a CMOS microcircuit can be applied to the input of a TTL microcircuit (taking into account that their supply voltages are the same). However, in the opposite direction, i.e., from TTL to CMOS, it is not recommended to run the signal.

Microcircuits are available in various packages. The most common types of cases are:

DIP
(Dual Inline Package)

The usual "cockroach". We push the legs into the holes on the board - and seal them.

The legs in the body can be 8, 14, 16, 20, 24, 28, 32, 40, 48 or 56.

The distance between the leads (pitch) is 2.5 mm (domestic standard) or 2.54 mm (for the bourgeoisie).

Lead width about 0.5 mm

Pin numbering - in the figure (top view). To determine the location of the first leg, you need to find the "key" on the body.

SOIC
(Small Outline Integral Circuit)

Planar microcircuit - that is, the legs are soldered on the same side of the board where the case is located. At the same time, the microcircuit lies with its belly on the board.

The number of legs and their numbering are the same as for DIP.

The pitch of the conclusions is 1.25 mm (domestic) or 1.27 mm (bourgeois).

Lead width - 0.33 ... 0.51

PLCC
(Plastic J-leaded Chip Carrier)

Square (less often - rectangular) body. The legs are located on all four sides, and are J-shaped (the ends of the legs are bent under the abdomen).

Microcircuits are either soldered directly to the board (planar), or inserted into the socket. The latter is preferable.

The number of legs is 20, 28, 32, 44, 52, 68, 84.

Legs pitch - 1.27 mm

Lead width - 0.66 ... 0.82

Pin numbering - the first leg near the key, increasing the number counterclockwise:

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Integrated microcircuits of transistor-transistor logic are microassemblies of a low degree of integration, built on bipolar transistors. Their main disadvantage is a small amount per crystal, as well as criticality to the supply voltage and a fairly large current consumption.

The diagram just above shows a simple logic gates - 3I - NOT... It is based on a conventional bipolar multi-emitter transistor VT1. The logic zero level at its output will appear in case of high levels on all three emitters at the same time. VT2 takes over the inverting function (NOT gate), and multi-emitter VT1 is a 3I logic gate.

Despite the listed disadvantages, the most popular TTL series, K155 is very popular today, look how many radio dummies you can collect on.

The K155 series is the largest TTL series. It contains more than 100 microassemblies performing various logical functions and operations (AND, OR, NOT, AND - NOT, OR - NOT, triggers, registers, counters, adders.

The level of a logical unit in microcircuits of this TTL series lies in the voltage range from 2.4 V to 5 V), and the level of a logical zero is not more than 0.4 V.

Almost all micro-assemblies in this series are available in a standard 14-pin package. With a dot or key notch marking the first pin. The 7th pin is the case or minus. 14 lying opposite the first is a plus.

The next step in the evolution of the K155 was the K555 series, in which the basic TTL principle was preserved, but added to the collector junctions of the transistors. Therefore, the K555 series was called TTLSh (TTL and Schottky diode). In TTLC, the power consumption has decreased by about 2 times, and the speed has increased dramatically.

CMOS ICs

The letter K at the beginning of the abbreviation stands for - complementary... In practice, this suggests that pairs with the same parameters are used in the microassembly, but one transistor has an n-type gate, and the other, respectively, p-type. They are also called CMOS (Complementary Metal-Oxide Semiconductor).

The figure shows an example of a classic basic logic gate NOT. That is, if one arrives at the input, then the output will already be a logical zero and vice versa.

Element 2I - NOT... From a couple of these logic gates it is easy to get, and from several triggers - a counter, a register and elementary memory devices.

And now about a fly in the ointment: at the maximum operating frequency, CMOS elements are noticeably inferior to other logic based on bipolar transistors (TTL) and they are offigenly sensitive to static electricity.

Microcircuits based on CMDP structures

Digital ICs based on CMDP structures are increasingly used in the development of various electronic circuits, for which there are very good reasons. KMDP IMS is a highly versatile and easily used device that has unique properties that are not typical for other classes of digital IMS.

These ICs are called complementary because they are made on the basis of CMDP transistors, i.e. based on pairs of field-effect transistors with the structure: metal - oxide (dielectric) - semiconductor, having very similar characteristics and channels of different types of conductivity. ICs built on this principle consume significantly less power from the power source than all other ICs and can operate in a wider range of supply voltage levels. Electronic wristwatches and car devices, medical electronic devices, television receivers, portable calculators are just a few examples of devices in which CMDP IMS are used.

The main advantages of digital ICs based on CMOS structures are a large input resistance of transistors (R in) 10 12 Ohm) and a high level of integration. When performing pulse devices on integrated logic elements of CMOS, the resistances of timing resistors are not limited from above due to high input resistances of transistors, therefore, to obtain pulses with a long duration, the electrical capacitance of timing capacitors should not be increased.

Complementary structures are complementary pairs of bipolar (p-n-p and n-p-n) or MIS (p-channel and n-channel) transistors, which can significantly improve the characteristics of the IC. They are made on a common substrate in pockets isolated from the substrate either by a p-n junction or by a dielectric film. Complementary transistors are made in the form of horizontal and vertical structures.

In transistors with a horizontal structure, the emitter, base, and collector are located on the same horizontal plane, therefore, minority carriers injected into the base move not perpendicular to the crystal surface, but along it. Such transistors are called end (lateral). In the manufacture of end

p-n-p transistors - the formation of emitters is carried out during the basic diffusion of n-p-n transistors. Then, through the second base diffusion, the emitter of the pnp transistor is surrounded by a collector. The base of the transistor is the original n-type semiconductor layer between these regions. The base width, therefore, and the value of the base current transfer coefficient are determined by the distance between the windows etched in the photo mode for the emitter and collector.

In vertical structures, the base is located under the emitter (injected minority carriers move in a direction perpendicular to the crystal surface). All three regions of the pnp transistor (collector, base and emitter) are formed by diffusion. Such complementary structures are difficult to manufacture due to the high precision requirements for the concentration of dopants. However, transistors made using this technology have a higher base current transfer coefficient than transistors with a horizontal structure and a high breakdown voltage of the collector junction.

The basis of CMOS elements is an inverter built on two complementary (complementary) MOS transistors ( n-MOS and p-MOS) with an isolated gate and an induced channel. A feature of this scheme ( fig. 4.17) is that the input voltage controls not only the key, but also the load transistor.

On fig. 4.5.2.the drain-gate characteristics of the used transistors are given. Transistor with n-channel ( VТ n) begins to conduct current if a positive voltage is applied to its gate, and a transistor with r-channel ( VT p) - if a negative voltage is applied to its gate with respect to the source.

It is important that both transistors have a "heel" in their drain-gate characteristics. Thus, if we want the circuit to work with a positive supply voltage (+ E P), then as a key transistor it is necessary to use VТ n, and as a load - VT p.

Figure: 4.17.1. CMOS inverter

Figure: 4.5.2. The gate characteristics of CMOS transistors

Inverter ( fig. 4.17) is constructed so that the source VT p is connected to E n,and the source VТ n - with the ground. Shutters VТ nand VT p are combined and serve as an input to the inverter, drains VТ nand VT p are also combined and serve as the output of the inverter. With this inclusion, the following formulas for determining the gate-source voltage will be valid VТ nand VT p: U zip \u003d U in, U zir \u003d U in -E p

U zip - gate-source voltage n-channel transistor ( VТ n);

U zir- gate-source voltage r-channel transistor ( VT p).

When considering the operation of the inverter, we will assume that VТ nand VT p have identical characteristics and the threshold voltage U Пп \u003d½ U Pr½ \u003d 1.5V.

U pp- threshold voltage n-channel transistor;

U Pr- threshold voltage p-channel transistor.

Consider the operation of a CMOS inverter according to its HVV ( fig. 4.18-a), on which four sections and dependencies can be distinguished U ZI = f(U BX) (fig. 4.18-b).

Section 1: U 0 in £ U Пп... Wherein U zip \u003d U in and VТ n closed, U zir \u003d U in - E p< U Prand VT p open.

Figure: 4.18. CMOS inverter specifications:
a) HVB, b) U SHUTTER-SOURCE \u003d f (U IN); c) I POTR \u003d f (U BX)

VТ nclosed), VT p is in deep saturation, the output will be a voltage close to E P ( U 1 OUT » E P).

Section II: U П\u003e U ВХ\u003e U Пп,

where U P - voltage at which the circuit switches

and U OUT \u003d 0.5 (U 1 - U 0). U SPTA \u003d U IN\u003e U Ppand VТ nstarts to open, U ЗИР \u003d U ВХ -Е П< U Пр and VT p is open.

On this site ½ U SPTA½ < ½ U ZIR½, therefore VT p will remain saturated and VТ n - in active mode.

VТ n.

The current flowing in the circuit creates a voltage drop across the channel VT p, due to this, the output voltage begins to decrease. However, with an increase in the input voltage in this section, the output voltage decreases slightly, since VT p is still saturated.

Dot U p: U VX \u003d U P \u003d 0.5E P;

U SPTA \u003d U IN \u003d U P\u003e U Ppand VТ n open; 0.5E P< U Пр and VT p is open.

At this point | U SPTA|=|U ZIR| therefore, the resistances of the channels of both transistors are also equal. Thus, the output will be a voltage equal to half the voltage of the power supply ( U OUT=0,5E P). This point corresponds to the vertical section on the characteristic. At this point, the circuit draws maximum current, since both transistors are on. At the slightest change in the input voltage, the output voltage changes dramatically.

Section III: E P -½ U Pr½ \u003e U IN\u003e U P; U SPTA= U IN\u003e U Pp and VТ nopen; U ЗИР \u003d U ВХ -Е П< U Пр and VT P is open, but with growth U BX is becoming less and less open.

On this site U SPTA\u003e|U ZIR|, and therefore VТ nis in saturation, a VT p - in active mode.

The current consumed by the circuit is determined in this case by the transistor VT p.

The output voltage in this section is equal to the voltage drop on the channel VТ n... Because VТ nis in saturation, then this drop is small, and with an increase U BX it decreases more and more.

Section IV: E p\u003e U in\u003e E p -½ U Pr½; U zip= U in\u003e U Pp and V nopen; U zir \u003d U in -E n\u003e U zipand VT p is closed.

In this state, the circuit practically does not consume current (since VT p is closed). VТ nis in deep saturation, while the output will have a voltage close to zero ( U out» 0).

As can be seen from HVB ( fig 4.5.1a), CMOS elements have good noise immunity. Noise immunity is equal to zero and one. This is because the switching point ( U in \u003d U P) lies exactly in the center of the input voltage range ( E P\u003e U in\u003e0). When E P \u003d + 5V, the maximum interference value can reach 1.5V. With growth E P the absolute noise immunity increases. The immunity of CMOS elements is approximately 30% of E P (U 0 in max"0.3 E P, U 1 in.min"0.7 E P).

Since the input of the CMOS inverter is MOS transistors with an insulated gate, the input impedance is very high (10 12 ¸ 10 13 Ohm). Therefore, such circuits practically do not consume current at the input.

The output impedance of CMOS circuits is small as in the Log state. 0 and in the Log state. 1, since one of the transistors VТ n or VT p will definitely be open. Thus, the output resistance is determined by the channel resistance of the open MOS transistor and is 10 2 ¸10 3 Ohm.

High input impedance and low output impedance result in a high static branching ratio at the output. The branching factor will be limited from above only by the speed requirements. Since each input of the circuit has a certain capacity, then with an increase in the branching ratio, the load capacity will increase, which, in turn, will increase the switching time of the element.

Thus, as the operating frequency decreases, the branching ratio will increase. In connection with the above, it is clear that the input and load characteristics lose their meaning. The load characteristic is only important when coupling CMOS elements with elements of other types.

The low output impedance of the element in both states allows the load capacitance to be quickly recharged. This results in fast turn-on and turn-off delays. In practice, the delay times are 50 ¸ 200 ns.

Figure: 4.5.1c explains the process of current consumption by the circuit.

In a static position, CMOS circuits consume very little current (10 -6 -10 -7 A).

Basically, current is consumed when switching a circuit, while U SPTAand ½ U ZIR½> U POR and both transistors VТ n and VT p open (sections II and III on CVB) However, the value of this current is less than that of TTL circuits, since the volume resistances of open MOS transistors exceed the resistances of open bipolar transistors. For this reason, there is no clipping resistor in CMOS circuits.

When switching the circuit, current is also consumed to charge the load capacitance. The magnitude of this current can be defined as I \u003d CEf П Where f P Is the switching frequency of the circuit.

The advantages of CMOS circuits also include the ability to operate at different supply voltages (3-15V). With an increase in the supply voltage, the absolute noise immunity will increase, however, the current consumption will also increase (sections II and III on the CVB will become wider). With a supply voltage of + 5V, the CMOS signal levels become compatible with the TTL levels.However, care must be taken to U 1 I / min for CMOS would be more E P - |U OL | for secure locking VT p... For this purpose, the TTL output is often connected through a resistor to E P.

The operation of CMOS circuits on TTL circuits is carried out, as a rule, through wiring diagrams.

On fig. 4.19the diagram of the basic element of the CMOS type is shown. The element implements the 4I-NOT function. The transistors are positioned in such a way that no through current will flow in the circuit for any combination of input signals. Elements of the OR-NOT type are constructed in a similar way. (fig.4.20).

In such circuits, due to the series connection of transistors in one of the arms, the output resistance increases in one of the states. Therefore, these elements have different on and off times. For the NAND element, the on time is longer than the off time, and for the NOR element, vice versa.

Figure: 4.19. Implementation of 4I-NOT function on CMOS

Figure: 4.20. Implementation of 4OR-NOT function on CMOS

Due to the very high input impedance, even a static charge can create a breakdown voltage. To protect against high-voltage charges of static electricity, there is a special protection circuit at the inputs of CMOS circuits (inside the microcircuit) (fig.4.21).

Figure: 4.21. CMOS Inverter with ESD Gate Protection

Diodes VD1, VD2 and VD3 protect the gate insulation from breakdown. Diodes VD4 and VD7 protect the inverter output from breakdown between r and n areas. Diodes VD5 and VD6 connected in series between the power rails to protect against accidental power polarity reversal.

Typical representatives of CMOS circuits are elements of the K564 series, which are characterized by the following parameters:

E P\u003d 3¸15V; U 0\u003d 0.01V (at E P\u003d 5V and I n=0); U 1\u003d 4.99V (at E P\u003d 5V and I n=0); I 0 in\u003d 0.2μA; I 1 in\u003d 0.2μA; I P\u003d 0.17mA (at E P\u003d 10V, F\u003d 100kHz and C n\u003d 50pF); t s\u003d 80ns; I 0 out\u003d 0.9mA (at U 0 out\u003d 0.5V and E P\u003d 10V); I 1 out\u003d 0.9mA (at U 1 out=E P-0.5V and E P\u003d 10V); C n \u003d200pF; With in\u003d 12pF.

An individual experiment (UIRS) requires special attention in preparation.

CMOS, Complementary-symmetry / metal-oxide semiconductor ) - technology for constructing electronic circuits. CMOS technology uses field effect transistors with an insulated gate with channels of different conductivity. A distinctive feature of CMOS circuits compared to bipolar technologies ( TTL , ESL and others) is a very low power consumption in static mode (in most cases, it can be assumed that energy is consumed only during state switching). A distinctive feature of the CMOS structure compared to other MOS structures ( N-MOS , P-MOS) is the presence of both n- and p-channel field-effect transistors; as a result, CMOS circuits are faster and less power efficient, but they are characterized by a more complex manufacturing process and lower packing density.

The vast majority of modern logical microcircuits , including, processors use CMOS circuitry.

History

Early CMOS circuits were very vulnerable to electrostatic discharge ... Now this problem has been largely solved, but when installing CMOS microcircuits, it is recommended to take measures to remove electrical charges.

For the manufacture of gates in CMOS cells in the early stages, aluminum ... Later, in connection with the emergence of the so-called self-aligned technology, which provided for the use of the shutter not only as a structural element, but at the same time as masks when obtaining drain-source regions, they began to use as a shutter polycrystalline silicon.

Technology

Scheme 2I-NOT

As an example, consider the circuit of a 2I-NOT gate, built using CMOS technology.

• If a high level is applied to both inputs A and B, then both transistors on the bottom of the circuit are open, and both upper ones are closed, that is, the output is connected to ground.
• If a low level is applied to at least one of the inputs, the corresponding transistor will be open at the top and closed at the bottom. Thus, the output will be connected to the supply voltage and disconnected from the ground.

There are no load resistances in the circuit, so in a static state, only leakage currents through closed transistors flow through the CMOS circuit, and the power consumption is very low. When switching, electrical energy is spent mainly on charging containers gates and conductors, so that the consumed (and dissipated) power is proportional to the frequency of these switching (for example, clock frequency processor).

Series of logic CMOS chips of foreign production

Series of logic CMOS chips of domestic production

• CMOS transistors (CMOS):
  • 164, 176, 561 and 564 correspond to the 4000 series, but 164 and 176 have only 9V supply;
  • 1554 - 74AC series;
  • 1561 - 4000B series;
  • 1564 - 74HC series;
  • 1594 - 74ACT series;
  • 5564 - 74HCT series;